Downsizing of wiring pitch has caused increase in wiring resistance and wiring capacitance. As a consequence, a problem of wiring delay has become significant. As a countermeasure thereto, low resistance wiring technology represented by copper wiring and the like, and low dielectric film represented by silicon oxide fluoride (the silicon oxide fluoride (SiOF) is referred to as FSG (Fluorine Silicate Glass) hereinafter), HSQ (Hydrogen Silsesquioxane) and the like, have been developed. In particular, FSG film is drawing attention in view of its compatibility with the conventional technology in view of its low dielectric property, which can be obtained by simply adding fluorine to a conventional silicon oxide film.
However, in the case in which the FSG film is used, there is a problem in which the wiring is peeled off during heat treatment thereof. This peeling is confirmed to occur in an interface between the wiring and insulating film containing fluorine after heat treatment. As an example thereof, a cross-section of a semiconductor device having its wiring formed in two layers is shown in FIG. 1.
As shown in FIG. 1, on a semiconductor substrate 111, a first insulating film 112 that does not contain fluorine is formed so as to cover a semiconductor element (for example, a transistor, DRAM or the like), which is not shown in the figure. A first wiring 113 is formed thereon including, from the bottom, a titanium (Ti) film, a titanium nitride (TiN) film, an aluminum copper (AlCu) film, a titanium (Ti) film and a titanium nitride (TiN) film. Then, a second insulating film 114 including a FSG film is formed in such a state to cover this first wiring 113. The second insulating film 114 including the FSG film is one that is formed by high density plasma CVD (CVD is an abbreviation of Chemical Vapor Deposition) method.
As a result, its film thickness differs depending on the width of the first wiring 113. In other words, the second insulating film 114 is formed thick on a first wiring 113w having broader width, and thin on a first wiring 113s having a narrower width.
On the second insulating film 114 including the above-mentioned FSG film is formed a third insulating film 115 with a silicon oxide film which is formed, for example, by the plasma CVD method, and the surface of the third insulating film 115 is flattened by a Chemical Mechanical Polishing (hereinafter, referred to as CMP). On this third insulating film 115 is formed a second wiring 117 having a likewise structure as that of the first wiring 113. Portions of the first wiring 113 and the second wiring 117 are connected via a tungsten plug 116. The semiconductor device 101 is thus constructed as described above.
However, when a sinter heat treatment is performed on the above-mentioned semiconductor device, for example, for one hour in a forming gas (nitrogen 96 vol. %, hydrogen 4 vol. %) atmosphere, for example, at 400° C., as shown in FIG. 2, a phenomenon that the second wiring 117 formed on the second insulating film 114 including the FSG is peeled is confirmed to occur. This phenomenon depends on its heat treatment period of time, and with an increasing heat treatment period of time, the peeling tends to worsen. This phenomenon as disclosed in Japanese Application Laid-Open No. Hei-8-321547 is estimated due to that free fluorine (F) in the FSG film is diffused externally during the heat treatment so as to react with titanium (Ti) which constitutes the bottom layer under the wiring and produce a titanium fluoride (TiF).
As a countermeasure, for example, as disclosed in the Japanese Application Laid-Open No. Hei.8-321547, there is a method for diffusing free fluorine present in the film to the external by applying annealing thereto after forming the FSG film. According to this method, because of an addition of the annealing process, if the process is increased, the electric resistance is increased due of application of heat to the wiring, thus generating the risk of deterioration of resistance properties against high temperature stress migration and the like. Further, as disclosed in Japanese Application Laid-Open No. Hei.10-326839, it is also considered to be an effective method for solving the above-mentioned problems to form an insulating cap film such as a SiO2 film thereon after polishing the surface of the interlayer insulating film by CMP. However, this method involves also an addition of the step of forming the SiO2 film.